Semiconductor memory devices having an array of non-volatile memory cells are well known in the art. Referring to FIG. 1, there is shown a semiconductor memory device 10 of the prior art. The device 10 comprises a memory array 12 of non-volatile memory cells arranged in a plurality of rows and columns. Each of the memory cells can be a split gate floating gate memory cell or a stacked gate floating gate non-volatile memory cell. A plurality of rows 14 and a plurality of columns 16 access the array of cells in the memory array 12. A high voltage generator 20 generates a high voltage which is used during the programming of one or more of the cells in the non-volatile memory array 12. The high voltage is supplied to a local pump 22 which comprises a PMOS transistor having a first terminal, a second terminal with a channel therebetween and a gate for controlling the conduction of the current from the first terminal to the second terminal. The gate of the transistor 22 is connected to a first terminal which receives the voltage from the high voltage generator 20. The local pump 22 has its second terminal connected to a source line 24. The source line 24 has resistance along the length thereof. As the line 24 extends further from the pump 22, the resistance increases. From the source line 24, a plurality of column access lines 26A-26N are connected to the plurality of column lines 16 which access the memory cells in the memory array 12. The device 10 also comprises a plurality of dummy column lines 30A-30N connected to the source line 24. The function of the dummy column lines 30(A-N) will be discussed hereinafter. Each of the column lines 16 has a MOS transistor 18 having a gate controlled by an input signal Data_i. Thus, the state of the voltage supplied to the gate of the MOS transistor 18, which is the state of the signal Data_i, determines whether the column line 16 connects the memory array 12 to the source line 24. Each of the MOS transistors connects the column line to a memory cell, which is a current source, where the amount of current flow differs depending upon the state to which the memory cell is programmed. Each of the dummy column lines 30(A-N) comprises a first MOS transistor 34A whose gate is supplied with the inverse of the data signal supplied to the column line 16, and a second MOS transistor 32A whose gate is connected to voltage source thereby acting as a current source.
In the operation of the memory device 10, during the programming mode, data that is desired to be programmed into the memory array 12 to selected cells, is supplied to the MOS transistors 18 to selectively turn on the selected column 16 to connect the memory array 12 to the source line 24 and ultimately to the high voltage from the high voltage generator 20. The problem, however, is that the data pattern supplied to the gate of the transistors 18 cannot be predicted. Thus, for a data pattern where Data_1=1, turning on the transistor 18A, and all the rest of the data signals Data_2 . . . Data_n−1 being turned off (equal 0) and Data_n=1, the current to the column 16N would be different than if the data pattern were Data_1=0, Data_2=0, Data_n−1=1, Data_n=1. This is because as previously stated, the source line 24 has resistance and as the column line 16 is located further away from the high voltage generator 20, more resistance is encountered, even though the same number of column lines 16 are turned on. Thus, the current supplied to the column line 16N for the memory cell furthest away from the high voltage generator 20 is different for the two cases, even although the two data patterns are the same in terms of the total amount of current lines being turned on. Furthermore, the data patterns may change. The total amount of current necessary to program the case where Data_1=1, Data_2=1, . . . Data_n=1 is very different from the case where the data pattern is Data_1=0, Data_2=0, . . . Data_n=0. The inconsistency between the current requirements between these two conditions further causes variations in the current load requirements on the high voltage generator 20.
In an effort to compensate for the difference in the data pattern as well as for the resistance in the source line 24, the dummy column lines 30A-30N are provided. Because the data pattern supplied to these dummy column lines is always the inverse of the data pattern supplied to the column line 16A-N, the total amount of current flowing through the source line 24 is the same irrespective of the actual data pattern supplied to the signals Data_1 . . . Data_n. In addition, because the current required during programming on the entire source line 24 is a constant, the resistance due to the source line 24 can be taken into account by the behavior of the MOS transistors in the column 16N furthest away from the high voltage generator 20.
Although the foregoing technique of compensating for the current requirements for different data patterns is satisfactory, as the scale of integration increases, because the pitch is reduced, the distance between column lines 16 to insert the dummy column lines 30 becomes increasingly difficult. Further, voltage drop could also increase because the pitch is smaller.
Therefore, it is desired to have a circuit and technique whereby the benefits of a constant data independent current limiting circuit can be implemented in a non-volatile memory array device.